Logic synthesis continues to play a critical role in Design Automation. The first paper presents a novel recursive approach to finding a minimal function that repersents a Boolean relationship. The second paper describes a fast technique for computing approximate CODCs for large circuits based on computing the CODCs of smaller sub-networks. The third paper discusses BDD-based functional decomposition into a cascasde of LUTs with intermediate outputs. The fourth paper proposes a novel algorithm to compute symmetries in incompletely specified functions. The final paper introduces new circuit restructuring techniques based on implicit enumeration of all possible restructuring patterns.